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FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 9 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
HPDC
2012
IEEE
11 years 9 months ago
VNET/P: bridging the cloud and high performance computing through fast overlay networking
networking with a layer 2 abstraction provides a powerful model for virtualized wide-area distributed computing resources, including for high performance computing (HPC) on collec...
Lei Xia, Zheng Cui, John R. Lange, Yuan Tang, Pete...
APPT
2009
Springer
14 years 2 months ago
Computational Performance of a Parallelized Three-Dimensional High-Order Spectral Element Toolbox
In this paper, a comprehensive performance review of an MPI-based high-order three-dimensional spectral element method C++ toolbox is presented. The focus is put on the performance...
Christoph Bosshard, Roland Bouffanais, Christian C...
IEEEPACT
2000
IEEE
13 years 12 months ago
Address Partitioning in DSM Clusters with Parallel Coherence Controllers
Recent research suggests that DSM clusters can benefit from parallel coherence controllers. Parallel controllers require address partitioning and synchronization to avoid handlin...
Ilanthiraiyan Pragaspathy, Babak Falsafi
DATE
2005
IEEE
104views Hardware» more  DATE 2005»
14 years 1 months ago
Queue Management in Network Processors
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
Ioannis Papaefstathiou, Theofanis Orphanoudakis, G...