80 search results - page 7 / 16 » High level synthesis for reconfigurable datapath structures |
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
Most existing high-level synthesis(HLS) systems attempt to generate a circuit from a behavioral description \out of the void", using the entire design space as the search dom...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
CODES
1996
IEEE
14 years 4 days ago
1996
IEEE
This reported work applies a transformational synthesis approach to hardware/software codesign. In this approach, the process of algorithm design is coupled early on with hardware...
JNSM
2010
13 years 2 months ago
2010
Cognitive Radio (CR) equipments are radio devices that support the smart facilities offered by future cognitive networks. Even if several categories of equipments exist (terminal,...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...