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ITNG
2007
IEEE
14 years 3 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
SAC
1996
ACM
14 years 1 months ago
An enabling optimization for C++ virtual functions
Gaining the code re-use advantages of object oriented programming requires dynamic function binding, which allows a new subclass to override a function of a superclass. Dynamic bi...
Bradley M. Kuhn, David Binkley
BMCBI
2004
132views more  BMCBI 2004»
13 years 9 months ago
Two-stage normalization using background intensities in cDNA microarray data
Background: In the microarray experiment, many undesirable systematic variations are commonly observed. Normalization is the process of removing such variation that affects the me...
Dankyu Yoon, Sung-Gon Yi, Ju-Han Kim, Taesung Park
ASPLOS
2008
ACM
13 years 11 months ago
Hardbound: architectural support for spatial safety of the C programming language
The C programming language is at least as well known for its absence of spatial memory safety guarantees (i.e., lack of bounds checking) as it is for its high performance. C'...
Joe Devietti, Colin Blundell, Milo M. K. Martin, S...
WWW
2005
ACM
14 years 10 months ago
A multi-threaded PIPELINED Web server architecture for SMP/SoC machines
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. D...