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MICRO
2010
IEEE
154views Hardware» more  MICRO 2010»
13 years 7 months ago
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
High density memory is becoming more important as many execution streams are consolidated onto single chip many-core processors. DRAM is ubiquitous as a main memory technology, but...
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. ...
DAC
2004
ACM
14 years 10 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
ICS
2003
Tsinghua U.
14 years 2 months ago
Selecting long atomic traces for high coverage
This paper performs a comprehensive investigation of dynamic selection for long atomic traces. It introduces a classification of trace selection methods and discusses existing and...
Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ron...
C++
1990
47views more  C++ 1990»
13 years 10 months ago
C++ and Operating Systems Performance: A Case Study
Vincent F. Russo, Peter Madany, Roy H. Campbell
MONET
2007
126views more  MONET 2007»
13 years 9 months ago
Performance Evaluation of a Power Management Scheme for Disruption Tolerant Network
Disruption Tolerant Network (DTN) is characterized by frequent partitions and intermittent connectivity. Power management issue in such networks is challenging. Existing power man...
Yong Xi, Mooi Choo Chuah, K. Chang