733 search results - page 10 / 147 » High performance in tree-based parallel architectures |
CCGRID
2006
IEEE
13 years 11 months ago
2006
IEEE
MPICH2 provides a layered architecture for implementing MPI-2. In this paper, we provide a new design for implementing MPI-2 over InfiniBand by extending the MPICH2 ADI3 layer. Ou...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper we discuss our initial experiences adapting OpenMP to enable it to serve as a programming model for high performance embedded systems. A high-level programming model...
INFOCOM
2003
IEEE
14 years 25 days ago
2003
IEEE
Abstract—Link bundling is a way to increase routing scalability whenever a pair of Label Switching Routers in MPLS are connected by multiple parallel links. However, link bundlin...
ISCAPDCS
2007
13 years 9 months ago
2007
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
CAMP
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per sec...