Sciweavers

733 search results - page 72 / 147
» High performance in tree-based parallel architectures
Sort
View
ISPAN
2005
IEEE
14 years 2 months ago
An FPGA-Based Floating-Point Jacobi Iterative Solver
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
Gerald R. Morris, Viktor K. Prasanna
ICPP
2008
IEEE
14 years 3 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
CASES
2008
ACM
13 years 11 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
SC
2009
ACM
14 years 3 months ago
Enabling high-fidelity neutron transport simulations on petascale architectures
The UNIC code is being developed as part of the DOE’s Nuclear Energy Advanced Modeling and Simulation (NEAMS) program. UNIC is an unstructured, deterministic neutron transport c...
Dinesh K. Kaushik, Micheal Smith, Allan Wollaber, ...
CLUSTER
2004
IEEE
14 years 19 days ago
An efficient end-host architecture for cluster communication
Cluster computing environments built from commodity hardware have provided a cost-effective solution for many scientific and high-performance applications. Likewise, middleware te...
Xin Qi, Gabriel Parmer, Richard West