64 search results - page 5 / 13 » High-Performance Extendable Instruction Set Computing |
HIPEAC
2010
Springer
13 years 9 months ago
2010
Springer
This paper presents a program generator for fast software Viterbi decoders for arbitrary convolutional codes. The input to the generator is a specification of the code and a single...
ICNP
2003
IEEE
14 years 22 days ago
2003
IEEE
CAMs are the most popular practical method for implementing packet classification in high performance routers. Their principal drawbacks are high power consumption and inefficient...
ISCA
1989
IEEE
13 years 11 months ago
1989
IEEE
: We explore the question: “What can a von Neumann processor borrow from dataflow to make it more suitable for a multiprocessor?’’ Starting with a simple, “RISC-like” ins...
IJCSA
2008
13 years 7 months ago
2008
Vector extensions for general purpose processors are an efficient feature to address the growing performance demand of multimedia and computer vision applications. Embedded proces...
ARITH
2001
IEEE
13 years 11 months ago
2001
IEEE
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...