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» High-Performance Extendable Instruction Set Computing
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HPCA
2000
IEEE
14 years 2 months ago
Improving the Throughput of Synchronization by Insertion of Delays
Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor...
Ravi Rajwar, Alain Kägi, James R. Goodman
ICRA
2010
IEEE
107views Robotics» more  ICRA 2010»
13 years 8 months ago
Fast resolution of hierarchized inverse kinematics with inequality constraints
— Classically, the inverse kinematics is performed by computing the singular value decomposition of the matrix to invert. This enables a very simple writing of the algorithm. How...
Adrien Escande, Nicolas Mansard, Pierre-Brice Wieb...
ASAP
2004
IEEE
127views Hardware» more  ASAP 2004»
14 years 1 months ago
A Public-Key Cryptographic Processor for RSA and ECC
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vi...
CORR
2010
Springer
89views Education» more  CORR 2010»
13 years 10 months ago
Power optimized programmable embedded controller
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
M. Kamaraju, K. Lal Kishore, A. V. N. Tilak
GECCO
2007
Springer
209views Optimization» more  GECCO 2007»
14 years 1 months ago
Hardware acceleration of multi-deme genetic algorithm for the application of DNA codeword searching
A large and reliable DNA codeword library is key to the success of DNA based computing. Searching for sets of reliable DNA codewords is an NP-hard problem, which can take days on ...
Qinru Qiu, Daniel J. Burns, Prakash Mukre, Qing Wu