290 search results - page 27 / 58 » High-Speed MARS Hardware |
WSCG
2003
13 years 9 months ago
2003
We present novel algorithms for efficient hierarchical collision detection and propose a hardware architecture for a single-chip accelerator. We use a hierarchy of bounding volum...
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— We present a back-illuminated 32 x 32 pixel SOI image sensor chip in 0.5-µm silicon-on-sapphire process capable of ultraviolet imaging. The imager performs ”snap-shot” ima...
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— This paper presents a passive filter for the front end of a high speed serial link receiver to aid timing recovery. The filter provides simultaneous lowpass and highpass tran...
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— We present a back-illuminated 32 x 32 pixel image sensor in 0.5-µm silicon-on-sapphire process. The imager performs ”snap-shot” image acquisition and analog readout at a c...
ICC
2007
IEEE
14 years 1 months ago
2007
IEEE
— This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at d...