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ACL
1990
15 years 4 months ago
A Hardware Algorithm for High Speed Morpheme Extraction and its Implementation
This paper describes a new hardware algorithm for morpheme extraction and its implementation on a specific machine (MEX-I), as the first step toward achieving natural language par...
Toshikazu Fukushima, Yutaka Ohyama, Hitoshi Miyai
RTAS
1997
IEEE
15 years 7 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
FCCM
2004
IEEE
112views VLSI» more  FCCM 2004»
15 years 6 months ago
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
ICCD
2006
IEEE
166views Hardware» more  ICCD 2006»
15 years 11 months ago
FPGA Implementation of High Speed FIR Filters Using Add and Shift Method
Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner