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» High-level design for asynchronous logic
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DFT
1999
IEEE
125views VLSI» more  DFT 1999»
13 years 12 months ago
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
John Lach, William H. Mangione-Smith, Miodrag Potk...
CDES
2008
90views Hardware» more  CDES 2008»
13 years 9 months ago
Nanocompilation for the Cell Matrix Architecture
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
Thomas Way, Rushikesh Katikar, Ch. Purushotham
CHES
2006
Springer
88views Cryptology» more  CHES 2006»
13 years 11 months ago
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage
Recent research has shown that cryptographers with glitches are vulnerable in front of Side Channel Attacks (SCA). Since then, several methods, such as Wave Dynamic Differential Lo...
Zhimin Chen, Yujie Zhou
TPDS
2010
109views more  TPDS 2010»
13 years 2 months ago
Incentivized Peer-Assisted Streaming for On-Demand Services
As an efficient distribution mechanism, Peer-to-Peer (P2P) technology has become a tremendously attractive solution to offload servers in large-scale video streaming applications. ...
Chao Liang, Zhenghua Fu, Yong Liu, Chai Wah Wu
EUROSSC
2007
Springer
14 years 1 months ago
Capturing Context Requirements
Context-aware applications require context information to adapt their behaviour to the current situation. When developing context-aware applications, application developers need to...
Tom Broens, Dick A. C. Quartel, Marten van Sindere...