Sciweavers

1773 search results - page 16 / 355
» High-level power estimation
Sort
View
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
15 years 6 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
112
Voted
NOMS
2000
IEEE
15 years 7 months ago
POWER prototype: towards integrated policy-based management
ot only high level description of abstract policy, but also enables such policy to be refined and eventually mapped into an appropriate configuration for controlling devices in the...
Marco Casassa Mont, Adrian Baldwin, Cheh Goh
JMLR
2010
160views more  JMLR 2010»
14 years 10 months ago
Neural conditional random fields
We propose a non-linear graphical model for structured prediction. It combines the power of deep neural networks to extract high level features with the graphical framework of Mar...
Trinh Minh Tri Do, Thierry Artières
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
15 years 8 months ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...
127
Voted
PERCOM
2005
ACM
16 years 2 months ago
Reducing the Calibration Effort for Location Estimation Using Unlabeled Samples
WLAN location estimation based on 802.11 signal strength is becoming increasingly prevalent in today's pervasive computing applications. As alternative to the wellestablished...
Xiaoyong Chai, Qiang Yang