111 search results - page 4 / 23 » High-level specification and efficient implementation of pip... |
CAISE
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. Mobile devices provide a variety of ways to access information resources available on the Web and a high level of adaptability to different aspects (e.g., device capabili...
ACSD
2005
IEEE
14 years 1 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
HIPEAC
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. On multi-core architectures with software-managed memories, effectively orchestrating data movement is essential to performance, but is tedious and error-prone. In this p...