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2002
IEEE
14 years 1 months ago
High Performance User Level Sockets over Gigabit Ethernet
While a number of User-Level Protocols have been developed to reduce the gap between the performance capabilities of the physical network and the performance actually available, a...
Pavan Balaji, Piyush Shivam, Pete Wyckoff, Dhabale...
SPAA
1996
ACM
14 years 29 days ago
From AAPC Algorithms to High Performance Permutation Routing and Sorting
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
Thomas Stricker, Jonathan C. Hardwick
GECCO
2007
Springer
209views Optimization» more  GECCO 2007»
14 years 21 days ago
Hardware acceleration of multi-deme genetic algorithm for the application of DNA codeword searching
A large and reliable DNA codeword library is key to the success of DNA based computing. Searching for sets of reliable DNA codewords is an NP-hard problem, which can take days on ...
Qinru Qiu, Daniel J. Burns, Prakash Mukre, Qing Wu
APCSAC
2006
IEEE
14 years 2 months ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
14 years 9 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal