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ISCAS
2011
IEEE
288views Hardware» more  ISCAS 2011»
13 years 13 days ago
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
Yang Sun, Guohui Wang, Joseph R. Cavallaro
ICPP
1997
IEEE
14 years 28 days ago
How Much Does Network Contention Affect Distributed Shared Memory Performance?
Most of recent research on distributed shared memory (DSM)systems have focused on either careful design of node controllersor cache coherenceprotocols. Whileevaluating these desig...
Donglai Dai, Dhabaleswar K. Panda
MICCAI
2005
Springer
14 years 9 months ago
Particle Filters, a Quasi-Monte Carlo Solution for Segmentation of Coronaries
Abstract. In this paper we propose a Particle Filter-based approach for the segmentation of coronary arteries. To this end, successive planes of the vessel are modeled as unknown s...
Charles Florin, Nikos Paragios, James Williams
SIPS
2008
IEEE
14 years 3 months ago
Efficient mapping of advanced signal processing algorithms on multi-processor architectures
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
Bhavana B. Manjunath, Aaron S. Williams, Chaitali ...
HIPC
2000
Springer
14 years 10 days ago
Memory Consistency and Process Coordination for SPARC Multiprocessors
Abstract. Simple and unified non-operational specifications of the three memory consistency models Total Store Ordering (TSO), Partial Store Ordering (PSO), and Relaxed Memory Orde...
Lisa Higham, Jalal Kawash