43 search results - page 3 / 9 » Hybrid Cache Architecture for High Speed Packet Processing |
ARVLSI
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
ICNP
2006
IEEE
14 years 1 months ago
2006
IEEE
— The phenomenal growth of the Internet in the last decade and society’s increasing dependence on it has brought along, a flood of security attacks on the networking and compu...
DDECS
2009
IEEE
14 years 2 months ago
2009
IEEE
—Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
PVLDB
2010
13 years 5 months ago
2010
Complex event detection is an advanced form of data stream processing where the stream(s) are scrutinized to identify given event patterns. The challenge for many complex event pr...