43 search results - page 4 / 9 » Hybrid Cache Architecture for High Speed Packet Processing |
ENGL
2008
13 years 7 months ago
2008
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated Annealing (SA). The proposed architecture achieves ...
SIGCOMM
2010
ACM
13 years 7 months ago
2010
ACM
Data-intensive applications that operate on large volumes of data have motivated a fresh look at the design of data center networks. The first wave of proposals focused on designi...
COMCOM
1998
13 years 7 months ago
1998
Using cable modems that operate at several hundred times the speed of conventional telephone modems, many cable operators are beginning to offer World Wide Web access and other da...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
With the growing number of programmable processing elements in today's MultiProcessor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware...
ANCS
2007
ACM
13 years 11 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...