Sciweavers

43 search results - page 5 / 9
» Hybrid Cache Architecture for High Speed Packet Processing
Sort
View
HIPC
1999
Springer
13 years 11 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
CF
2008
ACM
13 years 9 months ago
Multi-terabit ip lookup using parallel bidirectional pipelines
To meet growing terabit link rates, highly parallel and scalable architectures are needed for IP lookup engines in next generation routers. This paper proposes an SRAM-based multi...
Weirong Jiang, Viktor K. Prasanna
CCS
2011
ACM
12 years 7 months ago
MIDeA: a multi-parallel intrusion detection architecture
Network intrusion detection systems are faced with the challenge of identifying diverse attacks, in extremely high speed networks. For this reason, they must operate at multi-Giga...
Giorgos Vasiliadis, Michalis Polychronakis, Sotiri...
ANCS
2006
ACM
13 years 11 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo
NSDI
2008
13 years 9 months ago
Swift: A Fast Dynamic Packet Filter
This paper presents Swift, a packet filter for high performance packet capture on commercial off-the-shelf hardware. The key features of Swift include (1) extremely low filter upd...
Zhenyu Wu, Mengjun Xie, Haining Wang