121 search results - page 13 / 25 » Hybrid cache architecture with disparate memory technologies |
DELTA
2008
IEEE
13 years 8 months ago
2008
IEEE
As semiconductor technology advances, the performance gap between processor and memory has become one of the major issues in computer design. In order to bridge this gap, many met...
ICC
2007
IEEE
14 years 1 months ago
2007
IEEE
1 Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
ISCA
1994
IEEE
13 years 10 months ago
1994
IEEE
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
TC
2010
13 years 5 months ago
2010
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...