121 search results - page 14 / 25 » Hybrid cache architecture with disparate memory technologies |
MICRO
2003
IEEE
13 years 12 months ago
2003
IEEE
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...
WWW
2003
ACM
14 years 7 months ago
2003
ACM
Crawling the web is deceptively simple: the basic algorithm is (a) Fetch a page (b) Parse it to extract all linked URLs (c) For all the URLs not seen before, repeat (a)?(c). Howev...
ICPP
1991
IEEE
13 years 10 months ago
1991
IEEE
-- The Express Ring is a new architecture under investigation at the University of Southern California. Its main goal is to demonstrate that a slotted unidirectional ring with very...
RTAS
2006
IEEE
14 years 22 days ago
2006
IEEE
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...