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TABLEAUX
1998
Springer
14 years 1 months ago
Model Checking: Historical Perspective and Example (Extended Abstract)
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
Edmund M. Clarke, Sergey Berezin
DAC
1997
ACM
14 years 29 days ago
Remembrance of Things Past: Locality and Memory in BDDs
Binary Decision Diagrams BDDs are e cient at manipulating large sets in a compact manner. BDDs, however, are inefcient at utilizing the memory hierarchy of the computer. Recent ...
Srilatha Manne, Dirk Grunwald, Fabio Somenzi
ISLPED
1997
ACM
83views Hardware» more  ISLPED 1997»
14 years 29 days ago
A symbolic algorithm for low-power sequential synthesis
We present an algorithm that restructures the state transition graph STG of a sequential circuit so as to reduce power dissipation. The STG is modi ed without changing the behav...
Balakrishna Kumthekar, In-Ho Moon, Fabio Somenzi
VLSID
1996
IEEE
132views VLSI» more  VLSID 1996»
14 years 28 days ago
A study of composition schemes for mixed apply/compose based construction of ROBDDs
Reduced Ordered Binary Decision Diagrams ROBDDs have traditionally been built in a bottom-up fashion. In this scheme, the intermediate peak memory utilization is often larger than...
Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masah...
ICCAD
1994
IEEE
114views Hardware» more  ICCAD 1994»
14 years 27 days ago
Performance-driven synthesis of asynchronous controllers
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...
Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas ...