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DATE
2003
IEEE
104views Hardware» more  DATE 2003»
14 years 3 months ago
Symbolic Analysis of Nonlinear Analog Circuits
A new method is presented to model symbolically strongly nonlinear circuits, characterized by Piece-Wise Linear (PWL) functions. The method follows the idea of Bokhoven and Leenae...
Alicia Manthe, Zhao Li, C.-J. Richard Shi, Kartike...
ISCAS
2003
IEEE
122views Hardware» more  ISCAS 2003»
14 years 3 months ago
Reducing the number of variable movements in exact BDD minimization
Ordered Binary Decision Diagrams (BDDs) are frequently used in logic synthesis. In this paper a new exact BDD minimization algorithm is presented, which is based on state space se...
Rüdiger Ebendt
ISMVL
2002
IEEE
82views Hardware» more  ISMVL 2002»
14 years 2 months ago
Representations of Logic Functions Using QRMDDs
This paper considers quasi-reduced multi-valued decision diagrams with bits (QRMDD( )s) to represent twovalued logic functions. It shows relations between the numbers of nodes in ...
Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, ...
GECCO
2000
Springer
142views Optimization» more  GECCO 2000»
14 years 1 months ago
Improving EAs for Sequencing Problems
Sequencing problems have to be solved very often in VLSI CAD. To obtain results of high quality, Evolutionary Algorithms (EAs) have been successfully applied in many cases. Howeve...
Wolfgang Günther, Rolf Drechsler
ASPDAC
2005
ACM
142views Hardware» more  ASPDAC 2005»
13 years 12 months ago
Bridging fault testability of BDD circuits
Abstract— In this paper we study the testability of circuits derived from Binary Decision Diagrams (BDDs) under the bridging fault model. It is shown that testability can be form...
Junhao Shi, Görschwin Fey, Rolf Drechsler