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ASPDAC
2000
ACM
102views Hardware» more  ASPDAC 2000»
15 years 10 months ago
A hybrid approach for core-based system-level power modeling
Reducing power consumption has become a key goal for systemon-a-chip (SOC) designs. Fast and accurate power estimation is needed early in the design process, since power reduction...
Tony Givargis, Frank Vahid, Jörg Henkel
ICIP
2000
IEEE
16 years 7 months ago
Combined Spatial and Subband Block Coding of Images
This paper describes a low-memory cache efficient Hybrid Block Coder (HBC) for images in which an image subband decomposition is partitioned into a combination of spatial blocks a...
Frederick W. Wheeler, William A. Pearlman
ICCS
2005
Springer
15 years 11 months ago
Improved Tag Set Design and Multiplexing Algorithms for Universal Arrays
In this paper we address two optimization problems arising in the design of genomic assays based on universal tag arrays. First, we address the universal array tag set design probl...
Ion I. Mandoiu, Claudia Prajescu, Dragos Trinca
GLVLSI
2003
IEEE
239views VLSI» more  GLVLSI 2003»
15 years 11 months ago
A novel 32-bit scalable multiplier architecture
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable...
Yeshwant Kolla, Yong-Bin Kim, John Carter
EMNLP
2006
15 years 7 months ago
Extremely Lexicalized Models for Accurate and Fast HPSG Parsing
This paper describes an extremely lexicalized probabilistic model for fast and accurate HPSG parsing. In this model, the probabilities of parse trees are defined with only the pro...
Takashi Ninomiya, Takuya Matsuzaki, Yoshimasa Tsur...