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ISCA
1992
IEEE
151views Hardware» more  ISCA 1992»
14 years 1 months ago
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yos...
CGO
2008
IEEE
14 years 4 months ago
Compiling for vector-thread architectures
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...
Mark Hampton, Krste Asanovic
ISLPED
2003
ACM
86views Hardware» more  ISLPED 2003»
14 years 3 months ago
Exploiting compiler-generated schedules for energy savings in high-performance processors
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...
Madhavi Gopal Valluri, Lizy Kurian John, Heather H...
ISPDC
2007
IEEE
14 years 4 months ago
Hybrid MPI-Thread Parallelization of the Fast Multipole Method
We present in this paper multi-thread and multi-process parallelizations of the Fast Multipole Method (FMM) for Laplace equation, for uniform and non uniform distributions. These ...
Olivier Coulaud, Pierre Fortin, Jean Roman
IPPS
2005
IEEE
14 years 3 months ago
Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors
With the latest high-end computing nodes combining shared-memory multiprocessing with hardware multithreading, new scheduling policies are necessary for workloads consisting of mu...
Robert L. McGregor, Christos D. Antonopoulos, Dimi...