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ICS
1998
Tsinghua U.
14 years 25 days ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
SIGMOD
2004
ACM
262views Database» more  SIGMOD 2004»
14 years 8 months ago
The Next Database Revolution
Database system architectures are undergoing revolutionary changes. Most importantly, algorithms and data are being unified by integrating programming languages with the database ...
Jim Gray
HPDC
2008
IEEE
14 years 3 months ago
XenLoop: a transparent high performance inter-vm network loopback
Advances in virtualization technology have focused mainly on strengthening the isolation barrier between virtual machines (VMs) that are co-resident within a single physical machi...
Jian Wang, Kwame-Lante Wright, Kartik Gopalan
VEE
2005
ACM
218views Virtualization» more  VEE 2005»
14 years 2 months ago
The pauseless GC algorithm
Modern transactional response-time sensitive applications have run into practical limits on the size of garbage collected heaps. The heap can only grow until GC pauses exceed the ...
Cliff Click, Gil Tene, Michael Wolf
ISLPED
2004
ACM
151views Hardware» more  ISLPED 2004»
14 years 2 months ago
Dynamic voltage and frequency scaling based on workload decomposition
This paper presents a technique called “workload decomposition” in which the CPU workload is decomposed in two parts: on-chip and off-chip. The on-chip workload signifies the ...
Kihwan Choi, Ramakrishna Soma, Massoud Pedram