713 search results - page 75 / 143 » Hybrid transactional memory |
EUROPAR
2009
Springer
14 years 3 months ago
2009
Springer
The availability of large-scale computing platforms comprised of tens of thousands of multicore processors motivates the need for the next generation of highly scalable sparse line...
ICPADS
2006
IEEE
14 years 2 months ago
2006
IEEE
—Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. T...
HIPEAC
2009
Springer
14 years 18 days ago
2009
Springer
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
MASCOTS
2007
13 years 10 months ago
2007
—One of the biggest bottlenecks in desktop-based computing is the hard disk with I/O write latency being a key contributor. I/O write latency stems from the mechanical nature of ...
ISPD
2000
ACM
14 years 1 months ago
2000
ACM
In this paper, we present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing. The algorithm integrates the quadratic...