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ICCD
1995
IEEE
83views Hardware» more  ICCD 1995»
13 years 11 months ago
Concurrent timing optimization of latch-based digital systems
Many design techniques have been proposed to optimize the performance of a digital system implemented in a given technology. Each of these techniques can be advantageous in partic...
Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C...
DATE
2010
IEEE
147views Hardware» more  DATE 2010»
13 years 10 months ago
Detecting/preventing information leakage on the memory bus due to malicious hardware
An increasing concern amongst designers and integrators of military and defense-related systems is the underlying security of the individual microprocessor components that make up ...
Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok ...
ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
13 years 9 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III
ICDCS
2010
IEEE
13 years 9 months ago
CacheCast: Eliminating Redundant Link Traffic for Single Source Multiple Destination Transfers
Due to the lack of multicast services in the Internet, applications based on single source multiple destinations transfers such as video conferencing, IP radio, IPTV must use unica...
Piotr Srebrny, Thomas Plagemann, Vera Goebel, Andr...
CONEXT
2008
ACM
13 years 9 months ago
Cabernet: connectivity architecture for better network services
Deploying and managing wide-area network services is exceptionally challenging. Despite having servers at many locations, a service provider must rely on an underlying besteffort ...
Yaping Zhu, Rui Zhang-Shen, Sampath Rangarajan, Je...