20 search results - page 3 / 4 » Identification and Test Generation for Primitive Faults |
IOLTS
2000
IEEE
14 years 2 months ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
COMCOM
1999
13 years 9 months ago
1999
If a test does not produce the expected output, the incorrect output may have been caused by an earlier state transfer failure. Ghedamsi and von Bochmann [1992] and Ghedamsi et al...
VTS
1998
IEEE
14 years 2 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
VLSID
2005
IEEE
14 years 3 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
ICSE
2007
IEEE-ACM
14 years 10 months ago
2007
IEEE-ACM
Policy testing and analysis are important techniques for high assurance of correct specification of access control policies. We propose a set of testing and analysis techniques fo...