Sciweavers

305 search results - page 27 / 61
» Impact of Parallel Workloads on NoC Architecture Design
Sort
View
DSD
2006
IEEE
131views Hardware» more  DSD 2006»
13 years 11 months ago
Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
Christian Neeb, Norbert Wehn
PPOPP
2010
ACM
14 years 2 months ago
Load balancing on speed
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
Steven Hofmeyr, Costin Iancu, Filip Blagojevic
WWW
2005
ACM
14 years 8 months ago
A multi-threaded PIPELINED Web server architecture for SMP/SoC machines
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. D...
HPDC
2008
IEEE
13 years 7 months ago
File grouping for scientific data management: lessons from experimenting with real traces
Abstract-The analysis of data usage in a large set of real traces from a high-energy physics collaboration revealed the existence of an emergent grouping of files that we coined &q...
Shyamala Doraimani, Adriana Iamnitchi
IPPS
2009
IEEE
14 years 2 months ago
Understanding the design trade-offs among current multicore systems for numerical computations
In this paper, we empirically evaluate fundamental design trade-offs among the most recent multicore processors and accelerator technologies. Our primary aim is to aid application...
Seunghwa Kang, David A. Bader, Richard W. Vuduc