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ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
14 years 1 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
DNA
2009
Springer
173views Bioinformatics» more  DNA 2009»
14 years 2 months ago
Time-Complexity of Multilayered DNA Strand Displacement Circuits
Recently we have shown how molecular logic circuits with many components arranged in multiple layers can be built using DNA strand displacement reactions. The potential application...
Georg Seelig, David Soloveichik
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
14 years 8 months ago
Impact of NBTI on FPGAs
Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS...
Krishnan Ramakrishnan, S. Suresh, Narayanan Vijayk...
IEICET
2008
57views more  IEICET 2008»
13 years 7 months ago
Impact of Well Edge Proximity Effect on Timing
This paper studies impact of the well edge proximity effect on digital circuit delay, based on model parameters extracted from test structures in an industrial 65nm wafer process. ...
Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsum...
PARLE
1987
13 years 11 months ago
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a pr...
Peter H. Welch