ISQED 2005 - PDF Preprint Papers

ISQED 2005 International Symposium on Quality Electronic Design

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ISQED
2005
IEEE

169views Hardware» more ISQED 2005»

ASLIC: A Low Power CMOS Analog Circuit Design Automation

14 years 6 months ago

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This paper proposes an efﬁcient automation platform that provides fast and reliable path to analog circuit design for desired speciﬁcations. Circuit heuristics and hierarchy a...

Jihyun Lee, Yong-Bin Kim

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Id	Views	Title	Status

1	169	ASLIC: A Low Power CMOS Analog Circuit Design Automation	claim
2	162	Controlled-Load Limited Switch Dynamic Logic Circuit	claim
3	140	Toward Quality EDA Tools and Tool Flows Through High-Performance Computing	claim
4	133	Sensitivity-Based Gate Delay Propagation in Static Timing Analysis	claim
5	128	Reliability-Centric Hardware/Software Co-Design	claim
6	125	A New Method for Design of Robust Digital Circuits	claim
7	120	Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits	claim
8	119	Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery	claim
9	116	A Mask Reuse Methodology for Reducing System-on-a-Chip Cost	claim
10	112	Two-Dimensional Layout Migration by Soft Constraint Satisfaction	claim
11	108	Error Analysis for the Support of Robust Voltage Scaling	claim
12	106	Thermal-Aware Floorplanning Using Genetic Algorithms	claim
13	106	Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE	claim
14	99	Design Considerations for Low-Power Ultra Wideband Receivers	claim
15	98	A More Effective CEFF	claim
16	98	Wire Planning with Bounded Over-the-Block Wires	claim
17	95	Statistical Analysis of Clock Skew Variation in H-Tree Structure	claim
18	95	Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis	claim
19	95	Simulating and Improving Microelectronic Device Reliability by Scaling Voltage and Temperature	claim
20	92	Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays	claim
21	92	An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis	claim
22	91	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning	claim
23	90	Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment	claim
24	87	A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology	claim
25	84	Performance Driven OPC for Mask Cost Reduction	claim
26	81	Welcome Notes	claim
27	81	Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer	claim
28	81	An ILP Formulation for Reliability-Oriented High-Level Synthesis	claim
29	78	Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems	claim
30	78	Conference at a Glance	claim
31	78	Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction	claim
32	76	Technology Mapping for Reliability Enhancement in Logic Synthesis	claim
33	76	Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers	claim
34	68	Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization	claim
35	64	Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET	claim

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