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ASPLOS
2006
ACM
13 years 11 months ago
Instruction scheduling for a tiled dataflow architecture
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
ICPP
1998
IEEE
13 years 11 months ago
A memory-layout oriented run-time technique for locality optimization
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
Yong Yan, Xiaodong Zhang, Zhao Zhang
CASES
2006
ACM
14 years 1 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
ESOP
2011
Springer
12 years 11 months ago
Static Analysis of Run-Time Errors in Embedded Critical Parallel C Programs
We present a static analysis by Abstract Interpretation to check for run-time errors in parallel C programs. Following our work on Astr´ee, we focus on embedded critical programs ...
Antoine Miné
IPPS
1999
IEEE
13 years 11 months ago
A Factorial Performance Evaluation for Hierarchical Memory Systems
In this study, we introduce an evaluation methodology for advanced memory systems. This methodology is based on statistical factorial analysis. It is two fold: it first determines...
Xian-He Sun, Dongmei He, Kirk W. Cameron, Yong Luo