41 search results - page 2 / 9 » Impact of the Head-of-Line Blocking on Parallel Computer Net... |
ICDCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— Overlay routing has emerged as a promising approach to improving performance and reliability of Internet paths. To fully realize the potential of overlay routing under ...
PDP
2010
IEEE
13 years 11 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
PPOPP
2010
ACM
14 years 1 months ago
2010
ACM
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
ICDCS
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper evaluates the use of per-node multi-threading to hide remote memory and synchronization latencies in a software DSM. As with hardware systems, multi-threading in softwa...
PVM
2004
Springer
14 years 12 days ago
2004
Springer
Abstract. The ability to offload functionality to a programmable network interface is appealing, both for increasing message passing performance and for reducing the overhead on t...