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INFOCOM
2002
IEEE
14 years 17 days ago
Fair Scheduling and Buffer Management in Internet Routers
Abstract—Input buffered switch architecture has become attractive for implementing high performance routers and expanding use of the Internet sees an increasing need for quality ...
Nan Ni, Laxmi N. Bhuyan
BMCBI
2007
99views more  BMCBI 2007»
13 years 7 months ago
Flexible mapping of homology onto structure with Homolmapper
Background: Over the past decade, a number of tools have emerged for the examination of homology relationships among protein sequences in a structural context. Most recent softwar...
Nathan C. Rockwell, J. Clark Lagarias
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 1 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
ISPD
2005
ACM
174views Hardware» more  ISPD 2005»
14 years 1 months ago
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...
Chris C. N. Chu, Yiu-Chung Wong
ICDCSW
2003
IEEE
14 years 28 days ago
CATP: A Context-Aware Transportation Protocol for HTTP
— The rendering mechanism used in Web browsers have a significant impact on the user behavior and delay tolerance of retrieval. The head-of-line blocking phenomena prevents the ...
Huamin Chen, Prasant Mohapatra