248 search results - page 4 / 50 » Implementing Caches in a 3D Technology for High Performance ... |
IPPS
2005
IEEE
14 years 29 days ago
2005
IEEE
In 2002, Japan announced the Earth Simulator—a supercomputer based on low-volume vector processors and a custom network—and reported that computational scientists had used it ...
ICSE
2008
IEEE-ACM
14 years 8 months ago
2008
IEEE-ACM
The design and implementation of the reconstruction system in medical X-ray imaging is a challenging issue due to its immense computational demands. In order to ensure an efficien...
ICASSP
2008
IEEE
14 years 1 months ago
2008
IEEE
In this work, we implement a real-time visual tracker that targets the position and 3D pose of objects in video sequences, specifically faces. Using Stream Processors for perform...
CF
2007
ACM
2007
ACM
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
13 years 11 months ago
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward d...
ISCA
1989
IEEE
13 years 11 months ago
1989
IEEE
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...