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ASPLOS
2009
ACM
14 years 9 months ago
Maximum benefit from a minimal HTM
A minimal, bounded hardware transactional memory implementation significantly improves synchronization performance when used in an operating system kernel. We add HTM to Linux 2.4...
Owen S. Hofmann, Christopher J. Rossbach, Emmett W...
DATE
2005
IEEE
133views Hardware» more  DATE 2005»
14 years 2 months ago
Locality-Aware Process Scheduling for Embedded MPSoCs
Utilizing on-chip caches in embedded multiprocessorsystem-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work th...
Mahmut T. Kandemir, Guilin Chen
HICSS
2002
IEEE
116views Biometrics» more  HICSS 2002»
14 years 1 months ago
E-commerce Security Issues
Without trust, most prudent business operators and clients may decide to forgo use of the Internet and revert back to traditional methods of doing business. To counter this trend,...
Randy C. Marchany, Joseph G. Tront
ICPP
2009
IEEE
13 years 6 months ago
Cache-Efficient, Intranode, Large-Message MPI Communication with MPICH2-Nemesis
The emergence of multicore processors raises the need to efficiently transfer large amounts of data between local processes. MPICH2 is a highly portable MPI implementation whose l...
Darius Buntinas, Brice Goglin, David Goodell, Guil...
ICIP
2007
IEEE
14 years 3 months ago
Locally Competitive Algorithms for Sparse Approximation
Practical sparse approximation algorithms (particularly greedy algorithms) suffer two significant drawbacks: they are difficult to implement in hardware, and they are inefficie...
Christopher J. Rozell, Don H. Johnson, Richard G. ...