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VLSISP
2010
119views more  VLSISP 2010»
13 years 2 months ago
Hardware Acceleration of HMMER on FPGAs
We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for bio...
Steven Derrien, Patrice Quinton
CVIU
2010
267views more  CVIU 2010»
13 years 5 months ago
Accelerated hardware video object segmentation: From foreground detection to connected components labelling
This paper demonstrates the use of a single-chip FPGA for the segmentation of moving objects in a video sequence. The system maintains highly accurate background models, and integ...
Kofi Appiah, Andrew Hunter, Patrick Dickinson, Hon...
CODES
2006
IEEE
14 years 1 months ago
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines
In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylization...
Manjunath Kudlur, Kevin Fan, Scott A. Mahlke
ASAP
2009
IEEE
141views Hardware» more  ASAP 2009»
14 years 5 months ago
Accelerating a Virtual Ecology Model with FPGAs
—This paper describes the acceleration of virtual ecology models using field-programmable gate arrays (FPGAs). Our approach targets models generated by the Virtual Ecology Workb...
Julien Lamoureux, Tony Field, Wayne Luk
IJPP
2011
99views more  IJPP 2011»
13 years 2 months ago
Regular Lattice and Small-World Spin Model Simulations Using CUDA and GPUs
Data-parallel accelerator devices such as Graphical Processing Units (GPUs) are providing dramatic performance improvements over even multicore CPUs for lattice-oriented applicatio...
Kenneth A. Hawick, Arno Leist, Daniel P. Playne