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» Implementing the scale vector-thread processor
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IPPS
2008
IEEE
14 years 1 months ago
A simple power-aware scheduling for multicore systems when running real-time applications
High-performance microprocessors, e.g., multithreaded and multicore processors, are being implemented in embedded real-time systems because of the increasing computational require...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
IPPS
2009
IEEE
14 years 2 months ago
CellMR: A framework for supporting mapreduce on asymmetric cell-based clusters
The use of asymmetric multi-core processors with onchip computational accelerators is becoming common in a variety of environments ranging from scientific computing to enterprise...
M. Mustafa Rafique, Benjamin Rose, Ali Raza Butt, ...
ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
14 years 1 months ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
SIAMSC
2008
129views more  SIAMSC 2008»
13 years 7 months ago
Bottom-Up Construction and 2: 1 Balance Refinement of Linear Octrees in Parallel
Abstract. In this article, we propose new parallel algorithms for the construction and 2:1 balance refinement of large linear octrees on distributed memory machines. Such octrees a...
Hari Sundar, Rahul S. Sampath, George Biros
IPPS
2005
IEEE
14 years 1 months ago
MegaProto: A Low-Power and Compact Cluster for High-Performance Computing
“MegaProto” is a proof-of-concept prototype for our project “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, implementing our key idea that a mi...
Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sat...