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» Implicates and Reduction Techniques for Temporal Logics
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DAC
2001
ACM
14 years 8 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
CAV
2008
Springer
113views Hardware» more  CAV 2008»
13 years 9 months ago
Producing Short Counterexamples Using "Crucial Events"
Ideally, a model checking tool should successfully tackle state space explosion for complete system validation, while providing short counterexamples when an error exists. Techniqu...
Sujatha Kashyap, Vijay K. Garg
AIPS
2009
13 years 8 months ago
Flexible Execution of Plans with Choice
Dynamic plan execution strategies allow an autonomous agent to respond to uncertainties while improving robustness and reducing the need for an overly conservative plan. Executive...
Patrick R. Conrad, Julie A. Shah, Brian C. William...
ICFEM
2009
Springer
14 years 2 months ago
Scalable Multi-core Model Checking Fairness Enhanced Systems
Rapid development in hardware industry has brought the prevalence of multi-core systems with shared-memory, which enabled the speedup of various tasks by using parallel algorithms....
Yang Liu 0003, Jun Sun 0001, Jin Song Dong
JEI
2000
133views more  JEI 2000»
13 years 7 months ago
Low complexity block motion estimation using morphological-based feature extraction and XOR operations
Motion estimation is a temporal image compression technique, where an n x n block of pixels in the current frame of a video sequence is represented by a motion vector with respect...
Thinh M. Le, R. Mason, Sethuraman Panchanathan