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CODES
2003
IEEE
14 years 28 days ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
LCTRTS
1999
Springer
13 years 12 months ago
Optimizing for Reduced Code Space using Genetic Algorithms
Code space is a critical issue facing designers of software for embedded systems. Many traditional compiler optimizations are designed to reduce the execution time of compiled cod...
Keith D. Cooper, Philip J. Schielke, Devika Subram...
DM
2002
104views more  DM 2002»
13 years 7 months ago
A polynomial time algorithm for determining zero Euler-Petrie genus of an Eulerian graph
A dual-eulerian graph is a plane graph which has an ordering defined on its edge set which forms simultaneously an Euler circuit in the graph and an euler circuit in the dual grap...
Brigitte Servatius, Herman Servatius
ISSS
2000
IEEE
109views Hardware» more  ISSS 2000»
13 years 11 months ago
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors
The paper presents a novel software-pipelining algorithm suitable for optimizing compilers targeting embedded VLIW processors. The proposed algorithm is different from previous ap...
Cagdas Akturan, Margarida F. Jacome
NIPS
2007
13 years 9 months ago
Adaptive Embedded Subgraph Algorithms using Walk-Sum Analysis
We consider the estimation problem in Gaussian graphical models with arbitrary structure. We analyze the Embedded Trees algorithm, which solves a sequence of problems on tractable...
Venkat Chandrasekaran, Jason K. Johnson, Alan S. W...