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ISVLSI
2003
IEEE
97views VLSI» more  ISVLSI 2003»
14 years 1 months ago
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
Andrew B. Kahng, Bao Liu
CC
2008
Springer
193views System Software» more  CC 2008»
13 years 9 months ago
Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model
The polyhedral model provides powerful abstractions to optimize loop nests with regular accesses. Affine transformations in this model capture a complex sequence of execution-reord...
Uday Bondhugula, Muthu Manikandan Baskaran, Sriram...
EWC
2006
120views more  EWC 2006»
13 years 7 months ago
A comparison of two optimization methods for mesh quality improvement
We compare inexact Newton and block coordinate descent optimization methods for improving the quality of a mesh by repositioning the vertices, where the overall quality is measure...
Lori Freitag Diachin, Patrick M. Knupp, Todd S. Mu...
CSDA
2008
65views more  CSDA 2008»
13 years 7 months ago
Improving updating rules in multiplicative algorithms for computing D-optimal designs
In this paper we discuss a class of multiplicative algorithms for computing D-optimal designs for regression models on a finite design space. We prove a monotonicity result for a ...
Holger Dette, Andrey Pepelyshev, Anatoly A. Zhiglj...
ICCAD
2008
IEEE
122views Hardware» more  ICCAD 2008»
14 years 4 months ago
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Abstract— Power consumption has become a crucial problem in modern circuit design. Multiple Supply Voltage (MSV) design is introduced to provide higher flexibility in controllin...
Qiang Ma, Evangeline F. Y. Young