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DATE
2004
IEEE
126views Hardware» more  DATE 2004»
13 years 11 months ago
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
Montek Singh, Michael Theobald
ICDCS
2009
IEEE
14 years 4 months ago
FLASH: Fine-Grained Localization in Wireless Sensor Networks Using Acoustic Sound Transmissions and High Precision Clock Synchro
Sensor localization in wireless sensor networks is an important component of many applications. Previous work has demonstrated how localization can be achieved using various metho...
Evangelos Mangas, Angelos Bilas
EWSN
2006
Springer
14 years 7 months ago
On the Scalability of Routing Integrated Time Synchronization
Time synchronization is a crucial component of a large class of sensor network applications, traditionally implemented as a standalone middleware service that provides a virtual gl...
János Sallai, Branislav Kusy, Ákos L...
DAC
2009
ACM
14 years 2 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
TPDS
2010
176views more  TPDS 2010»
13 years 6 months ago
Coupling-Based Internal Clock Synchronization for Large-Scale Dynamic Distributed Systems
This paper studies the problem of realizing a common software clock among a large set of nodes without an external time reference (i.e., internal clock synchronization), any centr...
Roberto Baldoni, Angelo Corsaro, Leonardo Querzoni...