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GECCO
2005
Springer
152views Optimization» more  GECCO 2005»
14 years 1 months ago
Multi-level genetic algorithm (MLGA) for the construction of clock binary tree
The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorith...
Guofang Nan, Minqiang Li, Jisong Kou
WEA
2005
Springer
109views Algorithms» more  WEA 2005»
14 years 1 months ago
Synchronization Fault Cryptanalysis for Breaking A5/1
Abstract. A5/1 pseudo-random bit generator, known from GSM networks, potentially might be used for different purposes, such as secret hiding during cryptographic hardware testing, ...
Marcin Gomulkiewicz, Miroslaw Kutylowski, Heinrich...
DAC
2010
ACM
13 years 11 months ago
An efficient phase detector connection structure for the skew synchronization system
Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can ...
Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih...
DSN
2005
IEEE
14 years 1 months ago
Design Time Reliability Analysis of Distributed Fault Tolerance Algorithms
Designing a distributed fault tolerance algorithm requires careful analysis of both fault models and diagnosis strategies. A system will fail if there are too many active faults, ...
Elizabeth Latronico, Philip Koopman
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
14 years 4 months ago
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
— Clock meshes posses inherent low clock skews and excellent immunity to PVT variations, and have increasingly found their way to high-performance IC designs. However, analysis o...
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jia...