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PCI
2005
Springer
14 years 27 days ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
DATE
2008
IEEE
118views Hardware» more  DATE 2008»
13 years 9 months ago
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices
Advanced MOSFETs such as Strained Silicon (SS) devices have emerged as critical enablers to keep Moore's law on track for sub100nm technologies. Use of Strained Silicon devic...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
ANCS
2006
ACM
14 years 1 months ago
CAMP: fast and efficient IP lookup architecture
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been propos...
Sailesh Kumar, Michela Becchi, Patrick Crowley, Jo...
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Skew scheduling and clock routing for improved tolerance to process variations
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
BMCV
2000
Springer
13 years 11 months ago
The Perception of Spatial Layout in a Virtual World
The perception and recognition of spatial layout of objects within a three-dimensional setting was studied using a virtual reality (VR) simulation. The subjects' task was to d...
Heinrich H. Bülthoff, Chris Christou