Sciweavers

525 search results - page 92 / 105
» Improved Circular Layouts
Sort
View
LCTRTS
2010
Springer
13 years 10 months ago
An efficient code update scheme for DSP applications in mobile embedded systems
DSP processors usually provide dedicated address generation units (AGUs) to assist address computation. By carefully allocating variables in the memory, DSP compilers take advanta...
Weijia Li, Youtao Zhang
IOPADS
1996
100views more  IOPADS 1996»
13 years 9 months ago
ENWRICH a Compute-Processor Write Caching Scheme for Parallel File Systems
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...
Apratim Purakayastha, Carla Schlatter Ellis, David...
BMCBI
2010
154views more  BMCBI 2010»
13 years 8 months ago
An algorithm for automated closure during assembly
Background: Finishing is the process of improving the quality and utility of draft genome sequences generated by shotgun sequencing and computational assembly. Finishing can invol...
Sergey Koren, Jason R. Miller, Brian Walenz, Grang...
BMCBI
2006
125views more  BMCBI 2006»
13 years 8 months ago
Development of an open source laboratory information management system for 2-D gel electrophoresis-based proteomics workflow
Background: In the post-genome era, most research scientists working in the field of proteomics are confronted with difficulties in management of large volumes of data, which they...
Hiraku Morisawa, Mikako Hirota, Tosifusa Toda
TC
1998
13 years 8 months ago
Optimizing the Instruction Cache Performance of the Operating System
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
Josep Torrellas, Chun Xia, Russell L. Daigle