We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fai...
Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, Jame...
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. As a result, a paradigm shift from determ...
Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia W...
1 We have developed an approach to acquire complicated user optimization criteria and use them to guide iterative solution improvement. The eectiveness of the approach was tested ...
The scheduler is a key component in determining the overall performance of a parallel computer, and as we show here, the schedulers in wide use today exhibit large unexplained gap...
This paper presents a general model for estimating access times of serpentine tape drives. The model is used to schedule I/O requests in order to minimize the total access time. W...