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» Improvement of ASIC Design Processes
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ICCAD
1993
IEEE
134views Hardware» more  ICCAD 1993»
14 years 2 months ago
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
Jason Cong, Yuzheng Ding
WCE
2008
13 years 11 months ago
Design and Implementation of an E-Learning Model by Considering Learner's Personality and Emotions
Abstract Emotion, personality and individual differences are those effective parameters on human's activities such as learning. People with different personalities show differ...
Somayeh Fatahi, M. Kazemifard, Nasser Ghasem-Aghae...
IJMSO
2010
118views more  IJMSO 2010»
13 years 8 months ago
Dependencies between ontology design parameters
: Development and use of ontologies is increasing, but hampered by new challenges, such as determining which ontologies to reuse and which language to use. Ontology development met...
C. Maria Keet
EUROPAR
2008
Springer
13 years 11 months ago
Performance Implications of Cache Affinity on Multicore Processors
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...
Vahid Kazempour, Alexandra Fedorova, Pouya Alagheb...
ICS
2009
Tsinghua U.
14 years 4 months ago
Towards 100 gbit/s ethernet: multicore-based parallel communication protocol design
Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires ...
Stavros Passas, Kostas Magoutis, Angelos Bilas