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» Improvement of ASIC Design Processes
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124
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ICCAD
1993
IEEE
111views Hardware» more  ICCAD 1993»
15 years 7 months ago
Unifying synchronous/asynchronous state machine synthesis
We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized “bur...
Kenneth Y. Yun, David L. Dill
126
Voted
ICSM
1999
IEEE
15 years 8 months ago
Bunch: A Clustering Tool for the Recovery and Maintenance of Software System Structures
Software systems are typically modified in order to extend or change their functionality, improve their performance, port them to different platforms, and so on. For developers, i...
Spiros Mancoridis, Brian S. Mitchell, Yih-Farn Che...
218
Voted
DAC
2009
ACM
16 years 4 months ago
Contract-based system-level composition of analog circuits
Efficient system-level design is increasingly relying on hierarchical design-space exploration, as well as compositional methods, to shorten time-to-market, leverage design re-use...
Xuening Sun, Pierluigi Nuzzo, Chang-Ching Wu, Albe...
116
Voted
IROS
2006
IEEE
127views Robotics» more  IROS 2006»
15 years 9 months ago
A Pilot Study on Teleoperated Mobile Robots in Home Environments
– Mobile robots operating in home environments must deal with constrained space and a great variety of obstacles and situations to handle. This article presents a pilot study aim...
Daniel Labonte, François Michaud, Patrick B...
117
Voted
GLVLSI
2003
IEEE
173views VLSI» more  GLVLSI 2003»
15 years 9 months ago
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...