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» Improvement of ASIC Design Processes
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147
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PDP
2005
IEEE
15 years 9 months ago
Memory Bandwidth Aware Scheduling for SMP Cluster Nodes
Clusters of SMPs are becoming increasingly common. However, the shared memory design of SMPs and the consequential contention between system processors for access to main memory c...
Evangelos Koukis, Nectarios Koziris
132
Voted
ASPLOS
1998
ACM
15 years 8 months ago
Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors
Database applications such as online transaction processing (OLTP) and decision support systems (DSS) constitute the largest and fastest-growing segment of the market for multipro...
Parthasarathy Ranganathan, Kourosh Gharachorloo, S...
125
Voted
JCM
2007
115views more  JCM 2007»
15 years 3 months ago
eEPC: an EPCglobal-compliant Embedded Architecture for RFID-based Solutions
— Radio Frequency Identification (RFID) technology has a lot of potential to improve visibility across the supply chain and automate the business processes. This paper describes ...
Franco Fummi, Giovanni Perbellini
132
Voted
ICIP
2005
IEEE
16 years 5 months ago
Visual tracking using sequential importance sampling with a state partition technique
Sequential importance sampling (SIS), also known as particle filtering, has drawn increasing attention recently due to its superior performance in nonlinear and non-Gaussian dynam...
Yan Zhai, Mark B. Yeary, Joseph P. Havlicek, Jean-...
124
Voted
DAGM
2006
Springer
15 years 7 months ago
Optimizing Spectral Filters for Single Trial EEG Classification
We propose a novel spectral filter optimization algorithm for the single trial ElectroEncephaloGraphy (EEG) classification problem. The algorithm is designed to improve the classif...
Ryota Tomioka, Guido Dornhege, Guido Nolte, Kazuyu...