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» Improving Code Density Using Compression Techniques
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1999
Tsinghua U.
14 years 2 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
14 years 7 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman
GLOBECOM
2007
IEEE
14 years 4 months ago
Properties of Opportunistic and Collaborative Wireless Mesh Networks
Abstract—While the cost of nodes in a wireless mesh network is decreasing, the price tag of the network as a whole is best minimized by deploying the fewest number of nodes that ...
Cédric Westphal
GLOBECOM
2009
IEEE
14 years 1 months ago
Multi-User Cooperative Communications with Relay-Coding for Uplink IMT-Advanced 4G Systems
Adoption of relay stations has been commonly accepted as a key technique for future IMTadvanced 4G systems to improve the link performance. While study in relay systems is often c...
Lei Cao, Jinyun Zhang, Norio Kanno
LCTRTS
2007
Springer
14 years 4 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...